PORTC=0, XBARA=0, XBARB=0, PORTE=0, PORTA=0, LPTMR=0, PORTD=0, ENC=0, PORTB=0, ADC=0, AOI=0
System Clock Gating Control Register 5
| LPTMR | Low Power Timer Access Control 0 (0): Access disabled 1 (1): Access enabled |
| PORTA | Port A Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PORTB | Port B Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PORTC | Port C Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PORTD | Port D Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| PORTE | Port E Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| ENC | This bit controls the clock gate to the ENC module. 0 (0): Clock disabled 1 (1): Clock enabled |
| XBARA | XBARA Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| XBARB | XBARB Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| AOI | AOI Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| ADC | ADC Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |